1. Field of the Invention
The present invention relates to an integrated digital circuit capable of achieving desired performance free from influences by any variations in device characteristics due to variations of such as a threshold value, a gate length and the like of transistors as well as any variations in specification such as a resistance value and a capacitance value of a wiring line and the like and changes of operating environments such as temperature, current source voltage and the like, and capable of achieving desired performance by compensating for the skew of synchronized signal supplied to the synchronized circuit in the integrated digital circuit.
2. Prior Art
Conventional integrated digital circuits consist of a CMOS circuit complementarily operating nMOS transistors and pMOS transistors, and ECL circuit using bipolar transistors, a BiCMOS circuit using both circuits thereof and the like.
FIG. 1 is a block diagram showing one example of the construction for the conventional integrated digital circuit. Referring to FIG. 1, a semiconductor integrated circuit 1 integrated with the conventional digital circuits comprises an oscillation circuit 2 having a CMOS circuit or and ECL or a BiCMOS circuit, a processor 3 having the CMOS circuit or the ECL circuit or the BiCMOS circuit, an external signal input line 6, and an oscillation signal transfer line 7.
The processor 3 comprises at least two registers 4 synchronized with the oscillation signal transfer line 7 and a logic circuit 5 connected between the registers 4 to synthesize logic. The frequency of the oscillation signal generated by the oscillation circuit 2 is controlled by the signal input through the external signal input line 6. The oscillation signal is input to the processor 3 through the oscillation signal transfer line 7 and transformed to the synchronized signal of the registers 4 so as to synchronized the operation of the processor 3.
The signal input through the external signal input line 6 functions either as a control signal to control the frequency of the oscillation signal output from the oscillation circuit 2 or as synchronizing signal to minimize any difference in the phases of the external signal input to the integrated circuit 1 and the oscillation signal from the oscillation circuit 2. In the latter case, the oscillation circuit 2 generates the signal synchronized with the synchronized signal externally input. Some conventional integrated digital circuits do not include the oscillation circuit 2. In these circuits, the oscillation signal should be input to the processor 3 directly from the outside of the semiconductor integrated circuit 1.
For the oscillation circuit 2, both basic gate circuits either capable of changing the delay time by the external control signal or not capable of changing the delay time by the external control signal are used. On the other hand, only the basic gate circuits not capable of externally controlling the delay time is used for the logic circuit 5.
In cases, however, these conventional integrated digital circuit could not achieve the performance targeted during circuit designing, resulting from variations the device characteristics due to variations of such as the threshold value, the gate length and the like of the transistors as well as any variations in specification such as the resistance value and the capacitance value of the line and the like and changes of operating environments such as temperature, current source voltage and the like.
Therefore, the conventional integrated digital circuit had to be designed to have about two times more than the desired performance, considering indeterminate factors such as the aforementioned variations and changes. If such margin is not large enough, the yield of product having acceptable quality level may significantly decrease. Furthermore, due to the skew of synchronized signal arriving to the registers in the synchronized signal supplied to at least two registers forming the synchronized circuit in the aforementioned conventional integrated digital circuit, the integrated digital circuit had to be designed to have sufficient allowance for this skew.